The present disclosure relates to a semiconductor device. For example, the present disclosure relates to a semiconductor device including a plurality of CPU cores provided on one semiconductor chip.
A semiconductor device performs a final test for confirming that a product meets the specifications on all the products before shipment from the factory. However, even the products that passed this final test may have a defect found during a customer process. The defective products that pass another final test and found to be defective at customers are referred to as test escapes. The test escape that passes the final test but found to be defective is after all a defective product. It is thus necessary to incorporate a test process for detecting defects into the final test in order to prevent such products from being distributed in the market. To this end, the defect events occurring in the test escapes need to be analyzed. Japanese Unexamined Patent Application Publication No. 2010-176392 discloses an example of such an analysis method.
In the technique described in Japanese Unexamined Patent Application Publication No. 2010-176392, a debugger operates on a host PC, and two microprocessors A and B execute the same debugging operation via debug I/F devices A and B in parallel in accordance with an operation of the debugger. Then, internal information (dump result) acquired from the microprocessors A and B is transferred to the host PC, and the host PC 120 compares the internal information acquired from the microprocessors A and B to analyze the failure.